The International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design... more
The International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design methodologies of nanometer silicon systems on test and reliability. Power and thermal issues, leakage, process variations, susceptibility to environmental and operation-induced interference are physical constraints that drive the development of low-power, process-tolerant design techniques. However, these techniques generate a new set of test and reliability challenges, questing for an innovative set of methodologies and tools. You are invited to participate in LPonTR'10. Papers are invited that address current trends, challenges and proposed solutions in the following areas (but are not limited to): • Power and process variations aware design and test • Challenges of Ultra Low-power design on test and reliability • Design for Variability and its effec...
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Distributed Computing, Logic, Model Checking, Modeling, Productivity, and 15 moreComputer Hardware, Petri Nets, Communication System, Computer Software, Asynchronous circuit design, Protocols, Asynchronous Communication, Formal Specification, Formal Verification, Petri Net, Protocol Specification, Communication Protocol, Communication protocols, Logic Design, and Logic Synthesis
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Computer Architecture, Timing Analysis, VLSI, Automatic Control, Computer Hardware, and 10 moreElectronic Design Automation, Petri Nets, Asynchronous circuit design, State Space, Design optimization, Low Latency, Software Tool, Reference Point, Electrical And Electronic Engineering, and Place and Route
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Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state coding conflicts. The refinement process is generally done automatically using heuristics and often produces sub-optimal solutions, which... more
Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state coding conflicts. The refinement process is generally done automatically using heuristics and often produces sub-optimal solutions, which have to be corrected manually. This paper presents a framework for an interactive refinement process aimed to help the designer. It is based on the visualization of conflict cores, i.e., sets of transitions causing coding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.
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The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of... more
The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of resource allocation is a function of parameters of the active requests, which are assigned to the requests either statically or dynamically. This function can be defined
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Given the recent rise of the Internet-of-Things (IoT), networked devices are becoming deeply embedded into everyday objects, leading to a need for novel security methods. Physical Unclonable Functions (PUFs) enable the differentiation... more
Given the recent rise of the Internet-of-Things (IoT), networked devices are becoming deeply embedded into everyday objects, leading to a need for novel security methods. Physical Unclonable Functions (PUFs) enable the differentiation between instances of the same device and have the potential to replace costly cryptographic operations while providing higher security guarantees, due to their inherent unclonability. We present a pairwise, continuous authentication protocol based on Physical Unclonable Functions (PUFs) and supporting mutual authentication on resource constrained nodes. The unclonability provided by the PUFs is an integral part of the authentication process to continuously prove the existence of the PUF secrets and the proposed protocol is executed periodically to enable the establishment of trust between the participants. This is achieved by refreshing the authentication information in every protocol round, leading to a ‘CRP Ratchet’ mechanism of renewing the authenticating PUF challenge response pairs (CRPs). We also discuss the security and performance of the protocol in IoT applications with a large number of devices. Since the only operations used in the periodic protocol phase are hashing and exclusive OR, low computation, complexity, and energy consumption overhead is achieved.
The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used... more
The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used to avoid hazards, including data-dependent glitches, and in order to make switching activity data-independent (constant). The implementation uses a coarse pipeline architecture which is different from traditional
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This paper presents a new design flow for security using 1-of-n encoding. Initially high-level SystemC Galois descriptions are compiled into an intermediate format. The design flow passes though several stages of refinement, including... more
This paper presents a new design flow for security using 1-of-n encoding. Initially high-level SystemC Galois descriptions are compiled into an intermediate format. The design flow passes though several stages of refinement, including subfield-breakdown and change of basis, to generate small, regular logic blocks. These are converted into 1-of-n represention and subsequently passed to optimization and mapping tools for mapping to a new library of power-balanced components. The new library consists of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Finally logic optimization tools are applied to generate secure synchronous circuits for layout generation. The paper shows that the circuits generated are more efficient than those generated by alternative techniques.
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Checker designs for on-line testing of asynchronous handshake interfaces are proposed here. The checker monitors the interface signals that follow a protocol. The checker produces a code word at its output when the interface signals abide... more
Checker designs for on-line testing of asynchronous handshake interfaces are proposed here. The checker monitors the interface signals that follow a protocol. The checker produces a code word at its output when the interface signals abide to the protocol, where as, when the protocol is violated, a noncode word is generated at the output. Checkers are designed to directly implement sets of forbidden transitions, otherwise known as refusals. A “busy” approach is used to design the checker. In this approach, self-test of the checker is performed during the normal operation where the output signals are constantly switching.
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ABSTRACT State coding conflict detection is a fundamental part of the synthesis of asynchronous concurrent systems from their Signal Transition Graph (STG) specifications. This paper presents the extension of the method proposed earlier,... more
ABSTRACT State coding conflict detection is a fundamental part of the synthesis of asynchronous concurrent systems from their Signal Transition Graph (STG) specifications. This paper presents the extension of the method proposed earlier, the identification of state coding conflicts in STGs which is intended to work within a synthesis framework based on STG unfoldings. This approach has been implemented as a software tool using refined algorithms. A necessary condition detects state coding conflicts by using an approximate state covering approach. Being computationally efficient, this algorithm may generate false alarms. Thus a refinement technique is applied based on partial construction of the state space with extra computational cost. The experimental results demonstrating the efficiency of this approach are presented.
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With technology scaling, the vulnerability of combinational circuits is increased, so evaluating their reliability becomes an essential demand. In this paper a simple yet effective method is proposed to derive the reliability of a... more
With technology scaling, the vulnerability of combinational circuits is increased, so evaluating their reliability becomes an essential demand. In this paper a simple yet effective method is proposed to derive the reliability of a combinational circuit. The idea of this method is to prevent the complexity of the traditional methods that use multi-iteration statistical procedures. This goal is achieved by dividing the problem into two parts, one describing the cause of the error, and the other part is involved on the circuit under test. The cause of the error is represented as a stochastic model of the interference, which can be considered as a fixed model for a specific design. The other part is derived by applying the stochastic fault model on the circuit under test using a simulation tool. A critical values are obtained by the second part, these values are the boundaries between two regions; error region and error-free region. The next step is to find the probability of error-free...
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AbstractWe present a new design for a dual-rail & dual-spacer latch which exhibits totally symmetrical switching behaviour,which guarantees data independent power consumption and is therefore suitable for use in secure systems. We... more
AbstractWe present a new design for a dual-rail & dual-spacer latch which exhibits totally symmetrical switching behaviour,which guarantees data independent power consumption and is therefore suitable for use in secure systems. We comparethe simulation results with the latest security latches. 1 Introduction In recent years there has been an increased awareness of information technology security-related issues. More and morepeople are shopping and banking at home. The use of home and recreational computers has increased dramatically, andthe majority of these have Internet access to resources such as email, newsgroups and on-line shopping and banking.However, this has also increased the number of people with an ability to compromise data [1]. This has led to a very highpercentage of traffic that requires safeguarding. One of the most fundamental and widespread tools used in providingInternet security is encryption.Encryption based security algorithms are now widely used to protect dat...
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The application of asynchronous circuits has been restricted because of the lack of technology to test them. In this paper we introduce a technique to test circuits obtained by the direct mapping technique from 1-safe Petri nets.... more
The application of asynchronous circuits has been restricted because of the lack of technology to test them. In this paper we introduce a technique to test circuits obtained by the direct mapping technique from 1-safe Petri nets. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into the high-level specification, a Petri net. This technique uses a “pseudo clock” in order to handle the hazards which may occur under certain types of physical faults. The clock also helps to activate faults which exhibit themselves only under some particular arrangement of signals and to deliver the precise information about the fault location to the test point.
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ABSTRACT A new parameter of quantity fairness, or statistical fairness, describing behaviour of asynchronous arbiters is introduced. It takes into account timing parameters of the arbiter and its environment described as stochastic... more
ABSTRACT A new parameter of quantity fairness, or statistical fairness, describing behaviour of asynchronous arbiters is introduced. It takes into account timing parameters of the arbiter and its environment described as stochastic processes. In this context a traditional quality of fairness can be understood as a condition of having the probability of request serving equal to one under a uniform delay distribution in the range between 0 and infinity. Thus the new parameter can be treated as a generalisation of the common approach. The quantity fairness of an ordered arbiter, which stores requests in a FIFO in the order of their arrival, has been studied using stochastic Petri net technique. The experimental has been conducted using GreatSPN tool, which results show a significant fairness improvement of an ordered arbiter in comparison with the corresponding arbiter without a FIFO. The method of quantity fairness measurement in the GreatSPN environment has been developed.
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Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a... more
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method and the tool.
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A modified 4-slot asynchronous communication mechanism (ACM) using entirely selftimed circuits to implement the algorithm is presented here. Mutual exclusion elements are used to concentrate potential metastabilit y to a couple of... more
A modified 4-slot asynchronous communication mechanism (ACM) using entirely selftimed circuits to implement the algorithm is presented here. Mutual exclusion elements are used to concentrate potential metastabilit y to a couple of discrete points so that it can be resolved entirely within the mechanism itself, while the self-timed circuits allow the interface between the reader and writer processes and the mechanism to be minimised. Initial analyses show that this solution is more robust with regard to steering logic metastabilit y, and can potentially run faster, than the original 4-slot solution.
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This paper describes the development of a cell library which can be used to efficiently predict the distribution of circuit delay and leakage power performance due to process variation effects. In developing the library a stepwise... more
This paper describes the development of a cell library which can be used to efficiently predict the distribution of circuit delay and leakage power performance due to process variation effects. In developing the library a stepwise approach is adopted in which the effects of process variations on the design parameters of interest at the various levels of design abstraction are evaluated, that is from transistor through circuit to architectural level. A cell library is generated comprising functional blocks whose complexity ranges from a single gate up to several thousand gates. As a demonstration vehicle a 2-stage asynchronous micropipeline is simulated using the cell library to predict the subsequent delay and leakage power distributions. The experimental results show that the proposed method is much faster than the traditional statistical static delay/power analysis (SSTA/SPA) approaches by a factor of 50; the results are also compared with Monte Carlo simulation data for validation purposes, and show an acceptable error rate of within 5%.
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Cryptographic chips are highly susceptible to fault injection and power analysis attacks, which easily lets an attacker gain secret keys intended to be secure. In addition to these issues, testability circuitry is frequently manipulated... more
Cryptographic chips are highly susceptible to fault injection and power analysis attacks, which easily lets an attacker gain secret keys intended to be secure. In addition to these issues, testability circuitry is frequently manipulated to induce faults and undesired behavior. When power-balanced dual-rail (1-of-2) logic, a return-to-spacer protocol and power-balanced totally self checking checkers with redundant transistors are used together,
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... The main disadvantages of Hollaar's approach are the fun-damental mode assumptions and the use of local state vari-ables as outputs. ... The task of modify-ing the initial specification into a burst mode like model... more
... The main disadvantages of Hollaar's approach are the fun-damental mode assumptions and the use of local state vari-ables as outputs. ... The task of modify-ing the initial specification into a burst mode like model and its verification does not belong to the subject of this paper. ...
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ABSTRACT With increased reliance on encryption for e-commerce, communications and data storage, new techniques are constantly being developed to meet the demand for secure encryption systems requiring higher levels of security and... more
ABSTRACT With increased reliance on encryption for e-commerce, communications and data storage, new techniques are constantly being developed to meet the demand for secure encryption systems requiring higher levels of security and integrity. A significant aspect of integrity is the diffusion and avalanche effect, which is measured by its sensitivity to a single bit change between the cipher text and the plaintext. This effect should yield a catastrophic result which is measurable and can therefore be readily assessed for its suitability as part of a security system. This paper measures the standard one-dimensional implementations of the generalized new Mersenne number transform suite for its suitability in security applications. The generalized suite is expanded from the existing new Mersenne number transform, by the addition of two new transforms, which have yet to be fully assessed in this aspect. The two new transforms offer the same long power-of-two run lengths and efficient calculations over a field of integers modulo a Mersenne prime. Sharing similar characteristics with the original transform, they also have the cyclic-convolution property, suggesting that they too can wield significant impact in the fields of image-, signal-processing as well as cryptography.
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Asynchronous interfaces, being a popular way of dealing with timing closure problems in deep submicron SoCs, pose a serious problem for on-line testing. Their behavior is specified not as a traditional clocked automaton, but as an... more
Asynchronous interfaces, being a popular way of dealing with timing closure problems in deep submicron SoCs, pose a serious problem for on-line testing. Their behavior is specified not as a traditional clocked automaton, but as an asynchronous protocol with timing which depends on the clocks of the communicating blocks, wire and gate delays. The problem is exacerbated by the use
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ABSTRACT The authors present a novel circuit implementation of the advanced encryption standard using self-timed dual-rail technology. The design reduces leakage of internal information through balanced power consumption, which is... more
ABSTRACT The authors present a novel circuit implementation of the advanced encryption standard using self-timed dual-rail technology. The design reduces leakage of internal information through balanced power consumption, which is achieved by avoidance of glitches and by data-independent switching behaviour. The design utilises a pipeline structure with built-in controllers and novel, highly balanced security latches.
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ABSTRACT The most efficient power saving method in digital systems is to scale Vdd, owing to the quadratic dependence of dynamic power consumption. This requires memory working under a wide range of Vdds in terms of performance and power... more
ABSTRACT The most efficient power saving method in digital systems is to scale Vdd, owing to the quadratic dependence of dynamic power consumption. This requires memory working under a wide range of Vdds in terms of performance and power saving requirements. A self-timed 6T SRAM was previously proposed, which adapts to the variable Vdd automatically. However due to leakage, the size of memory is restricted by process variations. This paper reports a new self-timed 10T SRAM cell with bit line keepers developed to improve robustness in order to work in a wide range of Vdds down to 0.3V under PVT variations. In addition, this paper briefly discusses the potential benefits of the self-timed SRAM for designing highly reliable systems and detecting the data retention voltage (DRV).