Backgrounder

Download a new backgrounder now for detailed information on the Spectra-Q™ engine. Learn how the new engine provides more control and predictability at all stages of design planning and implementation. You will also learn how the Spectra-Q engine can help you tackle design productivity challenges by not only decreasing compile times, but also by reducing the total number of design iterations.

The Spectra-Q engine accelerates your time to market with 8X faster compile times and design iterations by providing:

• Faster algorithms (synthesis, placement, routing, timing analysis, and physical synthesis) that take advantage of  today’s multicore workstations
• Incremental flows that allow designers to re-enter a compiler stage and incrementally optimize portions of their design to significantly shorten design iterations
• The Rapid Recompile feature, which reuses synthesis and place-and-route information to streamline processing for small, incremental design changes, resulting in up to 3X faster compilation for pre-synthesis HDL changes and up to 4X faster compilation for post-fit SignalTap® II Logic Analyzer modifications
• Distributed compiles allows you to split your design and compile in parallel over multiple computers in a server farm, which dramatically reduces your overall compilation time

The Spectra-Q engine contains tools and capabilities that reduce the number of design iterations required to complete your FPGA and SoC design. 

• BluePrint Platform Designer—The BluePrint Platform Designer leverages the new Spectra-Q engine to explore a device’s peripheral architecture and efficiently assigns interfaces. BluePrint prevents illegal pin assignments by performing fitter and legal checks in real time, eliminating complex error messages and the need to wait for a full compile, speeding up your I/O design by 10X. Learn more about speeding up your I/O design using the BluePrint platform designer. 
• Hybrid Placer—The Spectra-Q engine also includes a new Hybrid Placement feature that uses advanced placement algorithms to speed up overall logic placement. The Hybrid Placer combines analytical and advanced annealing techniques for overall improved quality of results and a reduction in seed noise enabling faster timing closure.

The Spectra-Q engine fast-tracks design entry for hardware, software, and digital signal processing (DSP) designers. With multiple design entry methods, designers can target FPGAs with greater efficiency in their preferred design environment, including:

• C or C++ based—The Spectra-Q engine supports Altera’s new A++ Compiler for high-level synthesis to create intellectual property (IP) cores from C or C++, which significantly boosts productivity through faster simulation and IP generation.
• C based (OpenCL)—Software developers can use a familiar C-based design flow with the Altera® SDK for OpenCL. The SDK provides a software programming model and abstracts away the traditional FPGA hardware design flow.
  
• Model based—The DSP Builder tool supports a model-based design flow: you can generate HDL from your DSP algorithms directly from within the Simulink software.
• RTL based—The Quartus Prime software supports all standard languages, including SystemVerilog and VHDL-2008.

FPGA design software for the next-generation, multi-million logic element (LE) count devices such as Stratix® 10 FPGAs and SoCs requires a new approach. The Spectra-Q engine powers the Quartus Prime software to boost designer productivity and accelerate time to market for Stratix 10 devices.

Stratix 10 FPGAs and SoCs feature new hardware innovations specifically architected with the flexibility and modularity needed for true hierarchical design. Key features that have been co-optimized with the Spectra-Q engine for significantly higher productivity are:

• The new HyperFlex™ core architecture, with registers everywhere throughout the interconnect to achieve 2X the performance of previous generation FPGAs
• Programmable clock tree synthesis
• A sector-based approach to device configuration

The Spectra-Q engine takes advantage of this flexibility and modularity to dramatically reduce the number of design iterations, enable extensive design reuse, and facilitate architectural exploration and planning.