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Education & Language - Linguistics | Leakage in Nanometer CMOS Technologies

Leakage in Nanometer CMOS Technologies

Leakage in Nanometer CMOS Technologies

Narendra, Siva G.; Chandrakasan, Anantha P. (Eds.)

2006, X, 307 p. 207 illus.

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  • Hardcover, ISBN 978-0-387-25737-2

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    $149.00
  • Softcover, ISBN 978-1-4419-3826-8

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    $149.00
  • About this book

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles.

Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions.

Case studies supply real-world examples that reap the benefits of leakage power reduction solutions as the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

Content Level » Research

Related subjects » Circuits & Systems - Electronics & Electrical Engineering - Hardware - Information Systems and Applications - Nanotechnology

Table of contents / Sample pages 

Preface.- Taxonomy of Leakage: Sources, Impact, and Solutions.- Leakage Dependence on Input Vector.- Power Gating and Dynamic Voltage Scaling.- Methodologies for Power Gating.- Body Biasing.- Process Variation and Adaptive Design.- Memory Leakage Reduction.- Active Leakage Reduction and Multi-Performance Devices.- Impact of Leakage Power and Variation on Testing.- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors.- Case Study: Leakage Reduction in the Intel Xscale Microprocessor.- Transistor Design to Reduce Leakage.- Index.

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