Ultra-scaled MoS₂ transistors and circuits fabricated without nanolithography

Scaling of Si field-effect transistors (FETs) in integrated circuits is rapidly approaching physical limits [1–3]. The negative impact of the short-channel effects [4] on the performance of aggressively scaled Si FETs (with channel lengths  ∼20 nm) is currently mitigated by the use of very thin (<10 nm) Si channels, typically etched in the shape of fins [5]. Further downscaling of FETs would require even thinner channels, imposing a demand for atomically thin homogeneous semiconductor channels [6–8]. Two-dimensional semiconductor materials (e.g. monolayer MoS₂) are good candidates for such channels, because they are inherently atomically thin, have a uniform thickness, and are free from dangling bonds. Their application in the ultra-scaled FETs is limited mainly by the fabrication challenges because both the channel length ($L_{\rm ch}$) and gate length (L) of such FETs should be at the 10 nm scale. Ideally, the entire channel should be gated ($L_{\rm ch} = L$) to eliminate the ungated (access) parts of the channel.

After the first demonstration of the exfoliated monolayer MoS₂ FETs [9], there have been several attempts to integrate atomically thin MoS₂ channels in ultra-scaled FETs. Monolayer MoS₂ grown by chemical vapor deposition (CVD) has been used in FETs with $L \sim 10$ nm exhibiting drain currents $I_{\rm D} \sim 400$ A m⁻¹ (normalized by the channel width W), but with $L_{\rm ch} \sim 50$ nm [10]. Even shorter gate lengths ($L \sim 1$ nm) have been demonstrated in exfoliated multilayer MoS₂ FETs with carbon nanotube gates, albeit with $L_{\rm ch} \sim 500$ nm, and therefore lower I_D  ∼25 A m⁻¹ [11]. The technological challenge of realizing ultra-scaled FETs with $L_{\rm ch} \sim L$ could be overcome by fabricating FETs with self-aligned contacts in which the gate overlaps the source/drain contacts and covers the entire channel [12]. In this case, the physical gate length  >$L_{\rm ch}$, but it allows gating of the entire channel because $L_{\rm ch} = L$. Although such FETs are unsuitable for very high-frequency applications due to the overlap capacitances between the gate and the contacts, they could provide an insight into the operation of the ultra-scaled MoS₂ FETs. However, all ultra-scaled MoS₂ FETs which have been realized in this way so far were based on technologies which cannot be implemented on a large scale. Self-assembly of block copolymers has been used to fabricate back- gated MoS₂ FETs with L  ∼  7.5 nm, but required guiding Au lines and produced only multiple FETs connected in series [13]. Sub-10 nm top-gated MoS₂ FETs have also been realized, but only on top of cracks in Bi₂O₃ [14] or on widened grain boundaries of graphene [15].

Here we demonstrate 10 nm MoS₂ FETs fabricated on a large scale without high-resolution patterning. This was achieved by fabricating long-channel MoS₂ FETs by conventional lithography, and then reducing the length of the channel down to 10 nm by a shadow evaporation [16–21] of Au. The devices were fabricated on a local Al back gate with an ultra-thin high-k oxide (AlO_x) in order to efficiently gate the entire channel ($L_{\rm ch} = L$). Both multilayer exfoliated MoS₂ and monolayer MoS₂ grown by CVD were used in fabrication. The realized 10 to 20 nm MoS₂ FETs exhibit small hysteresis of current–voltage characteristics in air ambient, with drain current up to $I_{\rm D} \sim 560$ A m⁻¹ (for exfoliated multilayer MoS₂) and subthreshold swing $S_{\rm th} \sim 120$ mV dec⁻¹ (for CVD-grown monolayer MoS₂). We also realized n-type depletion load digital inverters with 10 nm MoS₂ FETs which exhibited high voltage gain ($A_{\rm v} \sim -50$) and input/output signal matching.

Fabrication of the ultra-scaled MoS₂ FETs is schematically depicted in figure 1. In the case of multilayer exfoliated MoS₂, a thin (25 nm) Al layer was initially evaporated on a standard SiO₂/Si substrate (figures 1(a)–(b)). The atomic force microscopy (AFM) image of one such substrate is shown in supporting information figure S1 (stacks.iop.org/TDM/7/015018/mmedia). The substrate was then exposed to air ambient to form a native oxide (AlO_x) at the top surface of Al [10, 12]. The native oxide layer had a thickness $t_{\rm ox} \sim 4$ nm and was used as a gate insulator. In the next step, MoS₂ was exfoliated on top of the AlO_x/Al gate stack (figure 1(c)). In order to reduce the overlap between the gate and source/drain contacts, the gate stack was then partially etched away, apart from the areas supporting the MoS₂ flakes (figure 1(d)). In the case of monolayer CVD-grown MoS₂ FETs, the gates were already patterned in the first step (figure 1(e)) and then CVD MoS₂ was transferred on top (figure 1(f)). The FET channel was then defined by etching the CVD MoS₂ (figure 1(g)).

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In both cases, the source and drain contacts, separated by  ∼1 $\mu$m, were subsequently fabricated by standard lithography, evaporating a thick layer (thickness h  =  60 nm) of Au (figure 1(h)). In the final step, a thin (22 nm) layer of Au was evaporated under tilt in order to create a small gap next to the contacts [18–21] which shadow the MoS₂ channels (figure 1(i)). The size of the gap was controlled by the evaporation angle $\alpha$ and the thickness of initial source and drain contacts (h). Therefore, the resolution of the initial lithographic process used to fabricate the initial source and drain contacts did not have any influence on the gap size. Gaps with the lengths L  =  $L_{\rm ch}$ between 10 and 20 nm were realized in this way.

Figure 2(a) shows a nanogap between the source and drain contacts in one of the exfoliated multilayer MoS₂ FETs, immediately after the shadow evaporation (large area images are shown in figures S2 and S3 and tilted images in figure S4). The edges of the contacts, defining the gap, are not perfectly smooth due to unavoidable imperfections in the profile of the developed resist (used in the lithographic process to define the initial source and drain contacts) and finite grain size of the evaporated Au film. These imperfections limit the minimum gap size to  ∼8 nm in contacts realized on exfoliated MoS₂. At smaller gap sizes (figure S5 shows a 5 nm gap), the material protruding across the gap (as in the encircled part of the gap shown in figure 2(a)) may coalesce and short-circuit the contacts. Even if not connected (as in figure 2(a)), such protrusions deteriorate the electrical properties of the FETs due to parasitic tunneling currents flowing between them. This is typically manifested in the reduction of the on/off ratio (figure 2(c)).

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The electrical properties of the FETs were improved by thermal annealing. Figure 2(b) shows the same section of the nanogap from figure 2(a) after annealing in vacuum. The protrusions which are not connected tend to recede to the corresponding contacts upon annealing, as evidenced by the encircled part of the gap in figure 2(b). Although this slightly increases the minimum gap size to  ∼10 nm on exfoliated MoS₂, it also significantly reduces the tunneling currents and improves the electrical properties of the FETs, as shown in figure 2(c). Annealed FETs exhibited  ∼10 times smaller drain off-current (due to reduced tunneling) but also higher drain on-current as annealing reduces the source and drain contact resistances [9]. This resulted in  ∼100 times larger drain on/off current ratio (which increased from 10³ to 10⁵) and a smaller subthreshold swing after annealing.

The output curves of the non-annealed FETs exhibited very poor drain current saturation (figure S6) due to parasitic tunneling currents which flow in parallel to the channel drain current. On the other hand, the annealed FETs exhibited a very good saturation for such short devices, with output conductance $g_{\rm d} \sim 10$ S m⁻¹ (normalized by the channel width W), as shown in figure 2(d) for $V_{\rm GS} < 1$ V. The measured drain current was up to $I_{\rm D} = 560$ A m⁻¹, which is the highest drain current for exfoliated multilayer MoS₂ FETs in air ambient to date, keeping in mind that multilayer FETs typically have higher current than monolayer FETs [10, 15, 22–30]. The largest transconductance was $g_{\rm m} = 662$ S m⁻¹ at $V_{\rm DS} = 2$ V and $V_{\rm GS} = 2.5$ V (figure 2(d)), while the highest intrinsic transistor gain was $A = g_{\rm m}/g_{\rm d} \sim 11$ on all output curves. The measured transconductance yields an extrinsic field-effect mobility $\mu \sim 3$ cm² V⁻¹s⁻¹. This estimated mobility is small because it includes the contribution of the contact resistance, as discussed in the Methods section. Despite small extrinsic mobility, the transconductance is comparable to that of graphene FETs with a gate length of  ∼1 $\mu$m [31] due to the very short channel used here.

The estimated extrinsic mobility in exfoliated multilayer MoS₂ FETs is comparable to that of short-channel devices made from exfoliated monolayer MoS₂ [14]. However, multilayer MoS₂ cannot fully follow the surface roughness of the gate (figure S8). This reduced the direct contact between the MoS₂ channel and the gate, which reduced the gate capacitance. The reduced gate capacitance leads to larger than expected [10, 13, 14, 32] subthreshold swing ($S_{\rm th} \sim 180$ mV dec⁻¹) and drain induced barrier lowering (∼230 mV V⁻¹).

The ultra-scaled FETs were also made of CVD-grown monolayer MoS₂ [33]. The minimum gap size in such FETs was between 10 and 20 nm (figures 3(a) and S9), which was larger than that of the exfoliated MoS₂ FETs. We found that use of CVD MoS₂ required larger initial gaps because annealing was less effective in eliminating the contact protrusions on CVD MoS₂. This is probably due to the pinning of protrusions on the imperfections in the CVD grown material and underlying roughness of the gate (which has more influence on the surface roughness of the CVD monolayer compared to the exfoliated multilayer MoS₂). However, CVD monolayer MoS₂ FETs were found to have larger drain current on/off ratio (∼10⁶) and smaller subthreshold swing ($S_{\rm th} \sim 120$ mV dec⁻¹) compared to the exfoliated multilayer MoS₂ FETs (figure 3(a)). This is due to the larger bandgap of monolayer MoS₂ with respect to multilayer MoS₂ and slightly larger gate length of the monolayer CVD-grown FETs. Use of CVD-grown material also allowed large-scale fabrication of FETs, which was not possible with the exfoliated material. However, there are limitations in the large-scale fabrication of the FETs, as discussed in the methods section and figure S10.

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The largest measured drain current in CVD monolayer MoS₂ FETs was $I_{\rm D} = 360$ A m⁻¹ (figure 3(b)), which is comparable to the highest drain current reported for such FETs [10], even though the latter were obtained by pulsed measurements in vacuum; here, the measurements were performed in air ambient without pulsing voltages. The largest transconductance was $g_{\rm m} = 170$ S m⁻¹ at $V_{\rm DS} = 2$ V and $V_{\rm GS} = 1.6$ V (figure 3(b)), which suggests an extrinsic field-effect mobility $\mu = 1.2$ cm² V⁻¹s⁻¹. In this case, the mobility was lower than that of the exfoliated multilayer FETs due to the additional processing step used to transfer MoS₂ from the growth substrate to the local back gates. This process (described in the methods section) is not required for top-gated FETs, which were fabricated directly on the growth substrate [10], and it deteriorated the quality of the transferred CVD monolayer MoS₂.

The ultra-scaled MoS₂ FETs were used to realize logic gates in the n-type depletion-load technology. Figure 4(a) shows the static voltage transfer characteristics of an exfoliated multilayer MoS₂ inverter. In most of the realized FETs, the threshold voltage was slightly negative ($V_{\rm th} \sim -0.2$ V) leading to a weak conduction of the load FET (the top FET in the inverter in figure 4(a)) in which $V_{\rm GS} = 0$ V. Besides, $V_{\rm th} \sim -0.2$ V results in the threshold voltage of the logic gates  <$V_{\rm DD}/2$. At large enough positive input voltages ($V_{\rm IN} > 0.4$ V), the driver FET (the bottom FET in the inverter) was therefore much more conductive than the load FET and the output voltage was approximately equal to zero, leading to a rail-to-rail operation. Small conductivity of the load FET and good saturation of the FETs led to a steep drop of the output voltage $V_{\rm OUT}$ as the input voltage $V_{\rm IN}$ is increased (at $V_{\rm IN} \sim 0.15$ V). This resulted in a large voltage gain $A_{\rm v}$∼ –50(figure 4(b)), which is remarkably high for such short devices.

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The threshold voltage of the logic gates, which was below $V_{\rm DD}/2$, prevented matching between the input and output signals, despite very high voltage gain. In addition, the current drive capabilities of the load FET were significantly reduced due to its poor conductivity. As a consequence, the realized logic gates could not be clocked above a few Hz, which is typical for this type of load FETs [34]. This problem was overcome by using more conductive load FETs at $V_{\rm GS} = 0$ V, i.e. the load FETs with a more negative threshold voltage. This is demonstrated in figure 4(c) which shows the digital waveforms measured in one of the inverters in which the load FET had $V_{\rm th} = -0.4$ V. Due to better conductivity of the load FET, the output voltage decreased slower as the input voltage was increased, effectively shifting the threshold voltage of the logic gates to  ∼$V_{\rm DD}/2$ (figure S12). Although this reduced the voltage gain and output voltage swing (and therefore increased the static power dissipation), it allowed signal matching, as shown in figure 4(c). In addition, a higher operating frequency was reached compared to that of the high-gain logic gates with low-conductivity load FETs [34], as demonstrated in figure 4(c). However, this frequency is still much smaller than the cutoff frequency of the highly conductive FETs (figure S13).

We have demonstrated a facile and scalable technique for the fabrication of ultrashort channel MoS₂ FETs which does not require nanolithography. The technique is general (i.e. it can be applied to any semiconductor transistor channel) and based on shadowing evaporated material by the standard prefabricated source and drain contacts. We realized both exfoliated multilayer and CVD-grown monolayer MoS₂ FETs in which the entire transistor channel, with a length between 10 and 20 nm, was gated. The realized MoS₂ FETs exhibit good drain current saturation demonstrating the suppression of short-channel effects in atomically thin transistors. The ultra-scaled MoS₂ FETs were used to realize logic gates in the n-type depletion-load technology with a voltage gain of  ∼−50. The load FETs with a higher current drive were used to improve the operating frequency and signal matching of the logic gates at the expense of the voltage gain. The tradeoff between the speed and voltage gain demonstrates a need for the implementation of the ultra-scaled FETs in future complementary metal-oxide-semiconductor (e.g. MoS₂) technology.

Degenerately doped Si chips with thermally grown 290 nm thick SiO₂ were used in the fabrication of the ultra-scaled MoS₂ FETs. Prior to the deposition of Al back-gates, the substrates were thoroughly cleaned in an acetone bath and rinsed with isopropanol. The gates were fabricated by thermal evaporation of 25 nm of Al in an e-beam evaporator at a base pressure of $1.2\times 10^{-6}$ mbar. After Al deposition, the samples were kept in air for one day to oxidize the top surface of Al. This created an Al/AlO_x gate stack with a gate oxide capacitance $C_{\rm ox} \sim 1.4$ $\mu$F cm⁻² [10, 35]. Although such native gate oxide has larger surface roughness than the underlying SiO₂ substrate (figure S1), we found that the gate leakage current did not have influence on the drain current (figures S7 and S11) if the gate oxide voltage was kept below 2.8 V. The typical gate oxide breakdown voltage was  ∼2.9 V.

Both exfoliated multilayer and CVD-grown monolayer MoS₂ were used in fabrication. Micromechanical exfoliation of MoS₂ (SPI supplies) was performed by a Scotch tape method directly on the substrates on which 25 nm of Al was previously evaporated (figure 1(c)). After exfoliation, MoS₂ flakes were located by an optical microscope and then characterized by an AFM (Veeco Innova) to find the thickness of the flakes. Due to a poor contrast of MoS₂ on Al, it was not possible to locate monolayer MoS₂ and therefore the flakes with thicknesses between 5 and 15 nm were used in device fabrication.

MoS₂ was grown directly on SiO₂ via solid-source CVD [27]. In particular, SiO₂ was treated with hexamethyldisilazane, and then decorated with  ∼25 $\mu$l of 100 $\mu$M perylene-3,4,9,10 tetracarboxylic acid tetrapotassium salt (PTAS). The substrate was placed face down on an alumina crucible with  ∼0.5 mg of MoO₃ powder, and loaded in to a tube furnace 30 cm downstream of  ∼100 mg of S powder. The tube was evacuated and flushed with Ar gas and brought back to atmospheric pressure. Temperature was ramped to 850 °C and held for 15 min with 30 sccm Ar flow, before being cooled to room temperature. After the growth, CVD MoS₂ was transferred from the growth substrate to the final substrate containing pre-patterned gates (figure 1(f)). Due to a strong adhesion of the CVD grown MoS₂ to the growth substrate, the transfer to the final substrate required evaporation of 60 nm of Au [36, 37] on MoS₂ and spin coating of a poly(methyl methacrylate) (PMMA) layer on top of Au. The resulting PMMA/Au/MoS₂ stack was picked up from the growth substrate by a polydimethylsiloxane (PDMS) stamp. Once the PMMA/Au/MoS₂ stack was detached from the growth substrate, it was placed on the final substrate. There, the entire stack was heated to 160 °C for 5 min to remove the PDMS stamp. PMMA was then removed in an acetone bath, followed by Au etching using KI:I solution (Sigma Aldrich). After etching of Au, the MoS₂ channel was defined by plasma etching using SF₆ (base pressure 80 mbar, flow rate 10 sccm, and power 50 W) for 25 s. A larger hysteresis and smaller mobility in CVD-grown monolayer MoS₂ FETs were attributed to the damaging effect of the transfer procedure.

All patterning was performed by e-beam lithography (Raith eLINE) at 10 kV using different types of PMMA (molecular weights between 250 000 and 950 000) as e-beam resists. However, high-resolution patterning was not required because the initially fabricated contacts had dimensions  ∼1 $\mu$m. Any other low-resolution method (e.g. conventional optical lithography) could have also been used in the fabrication of the initial contacts.

In the case of exfoliated MoS₂, Al surrounding the MoS₂ flakes was etched away (figure 1(d)) to reduce the overlap between the gate and source/drain contacts, i.e. to reduce the gate leakage current and parasitic components. Tetramethylammonium hydroxide was used for 15 s to completely etch away 25 nm of Al. After etching, the Al sample was kept in acetone for 2 h to remove the PMMA mask.

The initial 60 nm thick Au source and drain contacts (figure 1(h)) were fabricated by evaporating Au at a normal incidence in the e-beam evaporator at a base pressure  ∼$1.2\times 10^{-6}$ mbar. After fabricating the initial thick Au contacts, the second lithography process was used to define the pattern for thin Au contacts (figure 1(i)). A thinner layer of Au (22 nm) was deposited in the same e-beam evaporator, but this time the samples were tilted by $\alpha = 15^\circ$ with respect to the direction of the evaporated Au. The directionality of the e-beam evaporation process effectively increases shadowing [38, 39] both from the resist and thick contacts resulting in an oblique profile of the contacts, as discussed in figure S4.

The device fabrication was performed in parallel, i.e. all FETs on a wafer were fabricated at the same time. However, successful large-scale fabrication of the FETs also requires maintaining a constant gate length across a wafer. The gate length uniformity is affected by the thickness uniformity of the initial thick contacts deposited by e-beam evaporation [40]. The gate length uniformity of our process technology is discussed in figure S10 which demonstrates that a smoother substrate is required for better uniformity. Therefore, the successful large-scale fabrication of the FETs would require very smooth deposition of the gate material, e.g. by atomic layer deposition.

After the fabrication of nanogaps, the samples were annealed at 250 °C in vacuum (pressure  <$5\times 10^{-6}$ mbar) for 1 h. Annealing cleaned the nanogaps from protrusions and improved metal contact to MoS₂. Thermal annealing was performed in vacuum to prevent any damage to MoS₂ due to oxygen or humidity at higher temperature. The samples were heated to 250 °C at a rate of 10 °C min⁻¹. After annealing, the samples were allowed to spontaneously cool down to room temperature in vacuum.

The extrinsic field-effect mobility was estimated from the measured transfer curves. We fabricated both long ($L \sim 1$ $\mu$m) and short ($L \sim 10$ nm) channel exfoliated multilayer MoS₂ FETs on a global SiO₂/Si back gate as a reference. We found that typical extrinsic mobility in long channel FETs on SiO₂ was  ∼55 cm² V⁻¹s⁻¹ reducing down to ∼4 cm² V⁻¹s⁻¹ in short channel FETs. The reason for such small extrinsic mobility in short-channel devices is the contact resistance which is comparable to the resistance of short channels. The obtained value of  ∼4 cm² V⁻¹s⁻¹ on SiO₂ was close to  ∼3 cm² V⁻¹s⁻¹ obtained in short-channel devices on AlO_x.

All electrical measurements were performed in air ambient in FormFactor probe stations EP6 and Summit 11000. The electrical characterizations of the FETs and inverters were performed by Keithley 2611B source-measure units, a function generator (Tektronix AFG 3022B), and an oscilloscope (Keysight DS09064A). The small hysteresis in the samples was a consequence of adsorption of water from humidity in air [41–43] and charge traps in the gate oxide [44]. The SEM imaging was performed in Raith eLINE at 10 kV. The inverters were realized by externally connecting the fabricated FETs.

We thank Alexey Fedorov for support with thermal annealing. This research was supported by the EU H2020 Graphene Flagship Core 2 Grant No. 785219. RWG acknowledges support from the NSF Graduate Research Fellowship under Grant No. DGE-1656518. KS acknowledges partial support from the Stanford Graduate Fellowship (SGF) program and NSF Graduate Research Fellowship under grant No. DGE-114747.